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M16C/29 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0072-0030Z Rev.0.30 2004.06.15
1. Overview
The M16C/29 group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also contain a CAN module, makes it suitable for control of cars and LAN system of FA. In addition, they contain a multiplier and a DMAC, also making it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
Automotive body, safety & audio, LAN system of FA, etc.
------Table of Contents------
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
Rev.0.30 2004.06.15 REJ03B0072-0030Z
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/29 group 80-pin device. Table 1.2.2 lists performance outline of M16C/29 group 64-pin device. Table 1.2.1. Performance outline of M16C/29 group (80-pin device) Item Performance CPU Number of basic instructions 91 instructions 50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V) (Normal-ver./T-ver.) Shortest instruction excution time 100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V) (Normal-ver.) 50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105C) (V-ver.) 62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125C) (V-ver.) Operation mode Single chip mode Address space 1M bytes Memory capacity ROM/RAM : See the product list Peripheral port Input/Output : 71 lines function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels) Serial I/O 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus1, or IEbus2 2 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus1) A/D converter 10 bits x 27 channels DMAC 2 channels CRC calcuration circuit 2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable CAN module 1 channel 2.0B BOSCH compliant Watchdog timer 15 bits x 1 (with prescaler) Interrupt 28 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits (These circuits contain a built-in feedback * Main clock * Sub-clock resistor and external ceramic/quartz oscillator) * On-chip oscillator(main-clock oscillation stop detect function) * PLL frequency synthesizer Low voltage detection circuit Available (Normal-ver.) Not available (T-ver./V-ver.) Electrical Power supply voltage VCC=3.0V to 5.5V (f(BCLK)=20MHZ) (Normal-ver.) Characteristics VCC=2.7V to 5.5V (f(BCLK)=10MHZ) VCC=3.0V to 5.5V (T-ver.) VCC=4.2V to 5.5V (V-ver.) Power consumption 18mA (VCC=5V, f(BCLK)=20MHz) 25 A (VCC=5V, f(BCLK)=f(XCIN)=32KHz on RAM) 1.8 A (VCC=5V, f(BCLK)=f(XCIN)=32KHz, in wait mode) 0.8 A (VCC=5V, when stop mode) Flash memory Program/erase voltage 2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.) Number of program/erase 100 times ( Block A ,Block B : 10,000 times (option3) ) Operating ambient temperature -20 to 85C / -40 to 85C (option3) (Normal-ver.) -40 to 85C (T-ver.) -40 to 125C (V-ver.) Package 80-pin plastic mold QFP Notes: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a trademark of NEC Electronics Corporation. 3. If you desire this option, please so specify.
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Table 1.2.2. Performance outline of M16C/29 group (64-pin device) Item Performance CPU Number of basic instructions 91 instructions 50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V) (Normal-ver./T-ver.) Shortest instruction excution time 100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V) (Normal-ver.) 50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105C) (V-ver.) 62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125C) (V-ver.) Operation mode Single chip mode Address space 1M bytes Memory capacity ROM/RAM : See the product list Peripheral port Input/Output : 55 lines function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels) Serial I/O 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus1, or IEbus2 1 channel (SI/O3) Clock synchronous 1 channel (Multi-Master I2C bus1) A/D converter 10 bits x 16 channels DMAC 2 channels CRC calcuration circuit 2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable CAN module 1 channel 2.0B BOSCH compliant Watchdog timer 15 bits x 1 (with prescaler) Interrupt 28 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits (These circuits contain a built-in feedback * Main clock * Sub-clock resistor and external ceramic/quartz oscillator) * On-chip oscillator(main-clock oscillation stop detect function) * PLL frequency synthesizer Low voltage detection circuit Available (Normal-ver.) Not available (T-ver./V-ver.) Electrical Power supply voltage VCC=3.0V to 5.5V (f(BCLK)=20MHZ) (Normal-ver.) Characteristics VCC=2.7V to 5.5V (f(BCLK)=10MHZ) VCC=3.0V to 5.5V (T-ver.) VCC=4.2V to 5.5V (V-ver.) Power consumption 18mA (VCC=5V, f(BCLK)=20MHz) 25 A (VCC=5V, f(BCLK)=f(XCIN)=32KHz on RAM) 1.8 A (VCC=5V, f(BCLK)=f(XCIN)=32KHz, in wait mode) 0.8 A (VCC=5V, when stop mode) Flash memory Program/erase voltage 2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.) Number of program/erase 100 times ( Block A ,Block B : 10,000 times (option3) ) Operating ambient temperature -20 to 85C / -40 to 85C (option3) (Normal-ver.) -40 to 85C (T-ver.) -40 to 125C (V-ver.) Package 64-pin plastic mold QFP Notes: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a trademark of NEC Electronics Corporation. 3. If you desire this option, please so specify.
Rev.0.30 2004.06.15 REJ03B0072-0030Z
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/29 group, 80-pin device.
8
8
8
8
8
8
8
7
8
I/O Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer Timer A0 (16 bits) Timer A1 (16 bits) Timer A2 (16 bits) Timer A3 (16 bits) Timer A4 (16 bits) Timer B0 (16 bits) Timer B1 (16 bits) Timer B2 (16 bits) 3-phase PWM Timer S Input Capture (8 channels) Output Compare (8 channels) A/D converter (10bits x 27 channels) DMAC (2 channels) CRC arithmetic circuit (CCITT,CRC-16) Serial Ports U(S)ART/SIO (channel 0) U(S)ART/SIO (channel 1) U(S)ART/SIO/I 2C bus/IEBus (channel 2) SIO (channel 3) SIO (channel 4) Multi-master I C bus CAN module (1 channel)
2
System Clock Generator Xin-Xout Xcin-Xcout PLL frequency synthesizer On-chip Oscillator Watchdog Timer Low voltage detect
M16C/60 series 16-bit CPU Core
Program Counter Registers R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 FR FB SB R0L R0L R1L R1L PC Stack Pointers ISP USP Vector Table INTB Flag Register FLG Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Figure 1.3.2 is a block diagram of the M16C/29 group, 64-pin device.
4
3
8
4
8
8
8
4
8
I/O Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer Timer A0 (16 bits) Timer A1 (16 bits) Timer A2 (16 bits) Timer A3 (16 bits) Timer A4 (16 bits) Timer B0 (16 bits) Timer B1 (16 bits) Timer B2 (16 bits) 3-phase PWM Timer S Input Capture (8 channels) Output Compare (8 channels) A/D converter (10bits x 16 channels) DMAC (2 channels) Low voltage detect Serial Ports U(S)ART/SIO (channel 0) U(S)ART/SIO (channel 1) U(S)ART/SIO/I2C bus/IEBus (channel 2) SIO (channel 3) Multi-master I2C bus System Clock Generator Xin-Xout Xcin-Xcout PLL frequency synthesizer On-chip Oscillator Watchdog Timer
CRC arithmetic circuit (CCITT,CRC-16)
CAN module (1 channel)
M16C/60 series 16-bit CPU Core
Program Counter Registers R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 FR FB SB R0L R0L R1L R1L PC Stack Pointers ISP USP Vector Table INTB Flag Register FLG Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.4 Product List
Tables 1.4.1 to 1.4.3 list the M16C/29 group products and Figure 1.4.1 shows the type numbers, memory sizes and packages. Table 1.4.1. Product List (1) -Normal-ver. Type No. ROM capacity RAM capacity M30290F8HP (P) 64K + 4K byte 4K byte M30290FAHP (D) 96K + 4K byte 8K byte M30290FCHP (D) 128K + 4K byte 12K byte M30291F8HP (P) 64K + 4K byte 4K byte M30291FAHP (D) 96K + 4K byte 8K byte M30291FCHP (D) 128K + 4K byte 12K byte M30290M8-XXXHP (P) 64K byte 4K byte M30290MA-XXXHP (P) 96K byte 8K byte M30290MC-XXXHP (P) 128K byte 12K byte M30291M8-XXXHP (P) 64K byte 4K byte M30291MA-XXXHP (P) 96K byte 8K byte M30291MC-XXXHP (P) 128K byte 12K byte (P) : under planning (D) : under development As of Jun 2004 Remarks
Package type 80P6Q-A
Flash ROM Version 64P6Q-A
80P6Q-A Mask ROM Version 64P6Q-A
Table 1.4.2. Product List (2) -T-ver. Type No. ROM capacity RAM capacity Package type M30290F8THP (P) 64K + 4K byte 4K byte M30290FATHP (D) 96K + 4K byte 8K byte 80P6Q-A M30290FCTHP (D) 128K + 4K byte 12K byte M30291F8THP (P) 64K + 4K byte 4K byte M30291FATHP (D) 96K + 4K byte 8K byte 64P6Q-A M30291FCTHP (D) 128K + 4K byte 12K byte M30290M8T-XXXHP (P) 64K byte 4K byte M30290MAT-XXXHP (P) 96K byte 8K byte 80P6Q-A M30290MCT-XXXHP (P) 128K byte 12K byte M30291M8T-XXXHP (P) 64K byte 4K byte M30291MAT-XXXHP (P) 96K byte 8K byte 64P6Q-A M30291MCT-XXXHP (P) 128K byte 12K byte (P) : under planning (D) : under development NOTES: Specification of T-ver. partly varies from the one of Normal-ver. Table 1.4.3. Product List (3) -V-ver. Type No. ROM capacity RAM capacity Package type M30290F8VHP (P) 64K + 4K byte 4K byte M30290FAVHP (D) 96K + 4K byte 8K byte 80P6Q-A M30290FCVHP (D) 128K + 4K byte 12K byte M30291F8VHP (P) 64K + 4K byte 4K byte M30291FAVHP (D) 96K + 4K byte 8K byte 64P6Q-A M30291FCVHP (D) 128K + 4K byte 12K byte M30290M8V-XXXHP (P) 64K byte 4K byte M30290MAV-XXXHP (P) 96K byte 8K byte 80P6Q-A M30290MCV-XXXHP (P) 128K byte 12K byte M30291M8V-XXXHP (P) 64K byte 4K byte M30291MAV-XXXHP (P) 96K byte 8K byte 64P6Q-A M30291MCV-XXXHP (P) 128K byte 12K byte (P) : under planning (D) : under development NOTES: Specification of V-ver. partly varies from the one of Normal-ver.
Rev.0.30 2004.06.15 REJ03B0072-0030Z page 6 of 30
As of Jun 2004 Remarks
Flash ROM Version
Mask ROM Version
As of Jun 2004 Remarks
Flash ROM Version
Mask ROM Version
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Type No.
M 3 0 2 9 0 F 8 T H P - D3
Product code See Table 1.4.4 Product code Package type: HP : Package
80P6Q, 64P6Q
Version (no): Normal-ver. T : T-ver. V : V-ver. ROM capacity /RAM capacity: 6: (48K) bytes /4K bytes 8: (64K+4K) bytes (Note 1)/4K bytes A: (96K+4K) bytes (Note 1)/8K bytes C: (128K+4K) bytes (Note 1)/12K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type: M: Mask ROM version F: Flash memory version Show pin count 0: 80 pin version 1: 64 pin version M16C/29 Group M16C Family
Figure 1.4.1. Type No., Memory Size, and Package Table 1.4.4. Product code (Flash ROM Version, Normal-ver.) Internal ROM Block (0, 1, 2, 3) Internal ROM Block (A, B) Microcomputer Product Package operating Temperature Temperature Code E/W cycles E/W cycles temperature range range
D3 D5 D7 D9 U3 U5 U7 U9 LEAD free non-LEAD free
100
100
0C to 60C
-40C to 85C -20C to 85C
1,000 0C to 60C 100
10,000
-40C to 85C -40C to 85C -20C to 85C -20C to 85C
100
0C to 60C
-40C to 85C -20C to 85C
1,000
10,000
-40C to 85C -40C to 85C -20C to 85C -20C to 85C
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
(1) Flash ROM Version, 80P6Q-A, Normal-ver.
M16C M30290FAHP A D3 XXXXXXX Product Name : indicates M30290FAHP Chip Version and Product Code: A indicates chip version The first edition is shown to be blank and continues with A and B. D3 indicates product code (see Table 1.4.4) Date Code (7 digits) indicates manufacturing management code
(2) Flash ROM Version, 64P6Q-A, Normal-ver.
30291FA A D3 XXXXXXX Product Name : indicates M30291FAHP Chip Version and Product Code: A indicates chip version The first edition is shown to be blank and continues with A and B. D3 indicates product code (see Table 1.4.4) Date Code (7 digits) indicates manufacturing management code
Figure 1.4.2. Marking (Top View)
Rev.0.30 2004.06.15 REJ03B0072-0030Z
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.5 Pin Configuration
Figures 1.5.1 and 1.5.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)(Note)
P20/OUTC10/INPC10/SDAMM P21/OUTC11/INPC11/SCLMM
P17/INT5/INPC17/IDU
P22/OUTC12/INOC12
P23/OUTC13/INPC13
P24/OUTC14/INPC14
P25/OUTC15/INPC15
P26/OUTC16/INPC16
P27/OUTC17/INPC17
P15/INT3/ADTRG/IDV
P60/RTS0/CTS0
P16/INT4/IDW
P61/CLK0
42
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
41
P62/RxD0
P07/AN07
P10/AN20
P11/AN21
P12/AN22
P13/AN23
P14
P06/AN06 P05/AN05 P04/AN04 P03/AN03 P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P97/AN27/SIN4 P96/AN26/SOUT4
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P63/TxD0 P30/CLK3 P31/SIN3 P32/SOUT3 P33 P34 P35 P36 P37 P64/RTS1/CTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TxD1
{
P70/TxD2/SDA/TA0OUT /RTS1/CTS1/CTS0/CLKS1
P71/RxD2/SCL/TA0IN/CLK1 P72/CLK2/TA1OUT/V/RxD1 P73/CTS2/RTS2/TA1IN/V/TxD1 P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT
10
12
13
14
15
16
17
18
19
P90/AN30/TB0IN/CLKOUT
P84/INT2/ZP
P86/XCOUT
XOUT
P83/INT1
P92/AN32/TB2IN/CRX
P91/AN31/TB1IN
P82/INT0
VSS
P93/AN24/CTX
P80/TA4OUT/U
P87/XCIN
RESET
XIN
P85/NMI/SD
P81/TA4IN/U
VCC
Note. Set PACR2 to PACR0 bit in the PACR register to "011b" before you input and output it after resetting to each pin. When the PACR register isn't set up, the input and output function of some of the pins are disabled.
P95/AN25/CLK4
P77/TA3IN
CNVSS
20
11
1
2
3
4
5
6
7
8
9
Package: 80P6Q-A
Figure 1.5.1. Pin Configuration (Top View) of M16C/29 Group, 80-pin Package
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
PIN CONFIGURATION (top view)(Note)
P20/OUTC10/INPC10/SDAMM P21/OUTC11/INPC11/SCLMM
P17/INT5/INPC17/IDU
P22/OUTC12/INPC12
P23/OUTC13/INPC13
P24/OUTC14/INPC14
P25/OUTC15/INPC15
P26/OUTC16/INPC16
P27/OUTC17/INPC17
P15/INT3/ADTRG/IDV
P16/INT4/IDW
P60/RTS0/CTS0
P61/CLK0
P62/RxD0
34
40
39
38
37
36
35
48
47
46
45
44
43
42
P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P93/AN24/CTX P92/AN32/TB2IN/CRX
41
33
P63/TxD0
P03/AN03
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P30/CLK3 P31/SIN3 P32/SOUT3 P33 P64/RTS1/CTS1/CTS0/CLKS1 P65/CLK1 P66/RXD1 P67/TXD1
{
P70/TxD2/SDA/TA0OUT /RTS1/CTS1/CTS0/CLKS1
P71/RxD2/SCL/TA0IN/CLK1 P72/CLK2/TA1OUT/V/RxD1 P73/CTS2/RTS2/TA1IN/V/TxD1 P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT P77/TA3IN
10
12
13
14
15
XOUT
VSS
XIN
VCC
P84/INT2/ZP
P86/XCOUT
P83/INT1
P82/INT0
P87/XCIN
RESET
CNVSS
P91/AN31/TB1IN
Note. Set PACR2 to PACR0 bit in the PACR register to "010b" before you input and output it afer resetting to each pin. When the PACR register isn't set up, the input and output function of some of the pins are disabled.
P90/AN30/TB0IN/CLKOUT
P80/TA4OUT/U
P85/NMI/SD
P81/TA4IN/U
16
11
1
2
3
4
5
6
7
8
9
Package: 64P6Q-A
Figure 1.5.2. Pin Configuration (Top View) of M16C/29 Group, 64-pin Package
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.6 Pin Description
Table 1.6.1 and 1.6.2 describes the available pins. Table 1.6.1 Pin Description(1) Pin Name Signal name I/O type VCC,VSS Power supply input
CNVSS ____________ RESET XIN XOUT
CNVSS Reset input Clock input Clock output
Input Input Input Output
AVCC AVSS VREF P00~P07
Analog power supply input Analog power supply input Reference Input Voltage input I/O port P0 Input/Output
Function Apply 0V to the Vss pin, and the following voltage to the Vcc pin. 2.7 to 5.5V (Normal-ver.) 3.0 to 5.5V (T-ver.) 4.2 to 5.5V (V-ver.) Connect this pin to Vss. "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit input/ output. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. If XIN is not used (for external oscillator or external clock) connect XIN pin to VCC and leave XOUT pin open. This pin is a power supply input for the A/D converter. Connect this pin to VCC. This pin is a power supply input for the A/D converter. Connect this pin to VSS. This pin is a reference voltage input for the A/D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input, a pull-up register option can be selected for the entire group of four pins. Software can also select this port to function as A/D converter input pins. P04 to P07 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Additional software selectable secondary functions are: 1) P10 to P13 can act as A/D converter input pins; 2) P15 to P17 can be configured as external interrupt pins; 3) P15 to P17 can be configured as position-data-retain function input pins, and; 4) P15 can input a trigger for the A/D converter. P10 to P14 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Software can alse select this port to perform as I/O for the Timer S (all pins), and MultiMaster I2C Bus (P20 to P21 only). This is an 8-bit I/O port equivalent to P0. P30 to P32 also function as SIO3 I/O, as selected by software. P34 to P37 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O, as selected by software.
P10~P17
I/O port P1
Input/Output
P20~P27
I/O port P2
Input/Output
P30~P37
I/O port P3
Input/Output
P60~P67
I/O port P6
Input/Output
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Table 1.6.2 Pin Description(2) Pin Name Signal name I/O type P70~P77 I/O port P7 Input/Output
P80~P87
I/O port P8
Input/Output
P90~P93, P95~P97
I/O port P9
Input/Output
P100~P107
I/O port P10
Input/Output
Function This is an 8-bit I/O port equivalent to P0. P7 can also function as I/O for timer A0 to A3, as selected by software. Additional programming options are: P70 to P73 can assume UART1 or UART2 I/O capabilities, and P72 to P75 can function as output pins for the three-phase motor control timer. This is an 8-bit I/O port equivalent to P0. Additional software selectable secondary functions are: 1) P80 and P81 can act as either I/O for Timer A4, as output pins for the three-phase motor control timer; 2) P82 to P84 can be configured as external interrupt pins. P84 can be used for Timer A Zphase function; 3) P85 can be _______ _____ used as NMI/SD. P85 can not be used as I/O port while the threephase motor control is enabled. Apply a stable "H" to P85 after setting the direction register for P85 to "0" when the three-phase motor control is enabled, and; 4) P86 to P87 can serve as I/O pins for the subclock generation circuit. In this latter case, a quartz oscillator must be connected between P86 (XCOUT pin) and P87 (XCIN pin). This is an 7-bit I/O port equivalent to P0. Additional software selectable scondary functions are: 1) P90 to P92 can act as Timer B0 to B2 input pins; 2) P90 to P92 can act as A/D converter input pins; 3) P90 outputs a no division, divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by program; 4) P92 and P93 can function as I/O pins fpr the CAN module; 5) P93, P95 to P97 can act as A/D converter input pins, and; 6) P96 to P97 can assume SI/O4 I/O. P95 to P97 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. This port can also function as A/D converter input pins, as selected by software. Furthermore, P104 to P107 can also function as input pins for the key input interrupt function.
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
2. Central Processing Unit(CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2 R3
R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note) Frame base registers (Note)
b0
Data registers (Note)
b19
b15
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OB SZ DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
2. Central Processing Unit(CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate.
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/29 group. The linear address space of 1M bytes extends from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30290F8HP,there are 64 Kbytes of internal ROM from F000016 to FFFFF16. The vector table for fixed interrupts, such as Reset and NMI, is mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table register(INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30290FAHP, 8K bytes of internal RAM is mapped to the space from 0040016 to 023FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions. The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is allocated to the address from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual".
Internal RAM area Memory size 4K byte 8K byte 0000016 SFR area 0040016 Internal RAM area FFE0016 XXXXX16 RESERVED 0F00016 0FFFF16 Internal ROM area (data area) (Note1) Special page vector table 12K byte XXXXX16 013FF16 023FF16 033FF16
Internal ROM area Memory size 48K byte 64K byte 96K byte 128K byte YYYYY16 F400016 F000016 E800016 E000016
FFFDC16 RESERVED
Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset
YYYYY16 Internal ROM area (program area) FFFFF16
(Note2)
FFFFF16
Note 1 : The block A(2K bytes) and block B (2K bytes) are shown (only flash memory) Note 2 : When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1. Memory Map
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol
After reset
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 (Note 2)
PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0
0016 000010002 010010002 001000002 XXXXXX002 XX0000002 0X0000102 ??16 00??????2 (Note3) 0016 0016 X016 0016 0016 X016
Address match interrupt register 1
RMAD1
Voltage detection register 1 Voltage detection register 2 PLL control register 0 Processor mode register 2 Voltage down detection interrupt register DMA0 source pointer
(Note 4,5) (Note 4,5)
VCR1 VCR2 PLC0 PM2 D4INT SAR0
000010002 0016 0001X0102 XXX000002 0016 ??16 ??16 X?16 ??16 ??16 X/16 ??16 ??16
(Note 5)
DMA0 destination pointer
DAR0
DMA0 transfer counter
TCR0
DMA0 control register
DM0CON
00000?002
DMA1 source pointer
SAR1
??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16
DMA1 destination pointer
DAR1
DMA1 transfer counter
TCR1
DMA1 control register
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be used by users. Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. Note 3: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input voltage at the VCC pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1" (RAM retention limit detection circuit enable). Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 5: This registe can not use for T-ver. and V-ver. X : Nothing is mapped to this bit ? : Undefined
Figure 4.1. SFR Map (1 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register CAN0 wakeup interrupt control register CAN0 successful reception interrupt control register CAN0 successful transmission interrupt control register INT3 interrupt control register ICOC 0 interrupt control register ICOC 1 interrupt control register, I2C-BUS interface interrupt control register 1 ICOC base timer interrupt control register, SCL/SDA interrupt control register 2 SI/O4 interrupt control register, INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register CAN0 error interrupt control register A/D conversion interrupt control register, Key input interrupt control register (Note 2) UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register TimerA0 interrupt control register TimerA1 interrupt control register TimerA2 interrupt control register TimerA3 interrupt control register TimerA4 interrupt control register TimerB0 interrupt control register TimerB1 interrupt control register TimerB2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register CAN0 message box 0: Identifier/DLC
Symbol C01WKIC C0RECIC C0TRMIC INT3IC ICOC0IC
ICOC1IC,IICIC BTIC,SCLDAIC
After reset XXXX?0002 XXXX?0002 XXXX?0002 XX00?0002 XXXX?0002 XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XX00?0002 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16
S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC C01ERRIC ADIC, KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC
CAN0 message box 0 : Data field
CAN0 message box 0 : Time stamp CAN0 message box 1 : Identifier/DLC
CAN0 message box 1 : Data field
CAN0 message box 1 : Time stamp
Note 1: The blank areas are reserved and cannot be used by users. Note 2: A/D conversion interrupt control register is effective when the bit1(Interrupt source select register ( address 35Eh IFSR2A) is set to "0". Key input interrupt control register is effective when the bit1 is set to "1". X : Nothing is mapped to this bit ? : Undefined
Figure 4.2. SFR Map (2 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Register CAN0 message box 2: Identifier/DLC
Symbol
CAN0 message box 2 : Data field
CAN0 message box 2 : Time stamp CAN0 message box 3 : Identifier/DLC
CAN0 message box 3 : Data field
CAN0 message box 3 : Time stamp CAN0 message box 4: Identifier/DLC
CAN0 message box 4 : Data field
CAN0 message box 4 : Time stamp CAN0 message box 5 : Identifier/DLC
CAN0 message box 5 : Data field
CAN0 message box 5 : Time stamp
After reset XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.3. SFR Map (3 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Register CAN0 message box 6: Identifier/DLC
Symbol
CAN0 message box 6 : Data field
CAN0 message box 6 : Time stamp CAN0 message box 7 : Identifier/DLC
CAN0 message box 7 : Data field
CAN0 message box 7 : Time stamp CAN0 message box 8: Identifier/DLC
CAN0 message box 8: Data field
CAN0 message box 8 : Time stamp CAN0 message box 9 : Identifier/DLC
CAN0 message box 9 : Data field
CAN0 message box 9 : Time stamp
After reset XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.4. SFR Map (4 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16
Register CAN0 message box 10: Identifier/DLC
Symbol
CAN0 message box 10 : Data field
CAN0 message box 10 : Time stamp CAN0 message box 11 : Identifier/DLC
CAN0 message box 11 : Data field
CAN0 message box 11 : Time stamp CAN0 message box 12: Identifier/DLC
CAN0 message box 12: Data field
CAN0 message box 12 : Time stamp CAN0 message box 13 : Identifier/DLC
CAN0 message box 13 : Data field
CAN0 message box 13 : Time stamp
After reset XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.5. SFR Map (5 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116
Register CAN0 message box 14: Identifier/DLC
Symbol
CAN0 message box 14 : Data field
CAN0 message box 14 : Time stamp CAN0 message box 15 : Identifier/DLC
CAN0 message box 15 : Data field
CAN0 message box 15 : Time stamp CAN0 global mask register C0GMR
CAN0 local mask A register
C0LMAR
CAN0 local mask B register
C0LMBR
After reset XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 X?16 XX??????2 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 XX??????2 XX??????2 ??16 X?16 XX16 XX??????2 XX??????2 XX??????2 ??16 X?16 XX16 XX??????2 XX??????2 XX??????2 ??16 X?16 XX16 XX??????2
~
01B316 01B416 01B516 01B616 01B716
~
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 (Note 2) (Note 2) (Note 2) FMR4 FMR1 FMR0 0100000X2 000???0?2 0116
~ ~
01FD16 01FE16 01FF16
~ ~
Note 1: The blank areas are reserved and cannot be used by users. Note 2: This register is included in the flash memory version. X :Nothing is mapped to this bit ? : Undefined
Figure 4.6. SFR Map (6 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16
Register CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 CAN0 control register CAN0 status register CAN0 slot status register CAN0 interrupt control register CAN0 extended ID register CAN0 configuration register CAN0 receive error count register CAN0 transmit error count register CAN0 time stamp register
Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR
After reset 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X00000012 XX0X00002 0016 X00000012 0016 0016 0016 0016 0016 0016 ??16 ??16 0016 0016 0016 0016
~
024216 024316
~
CAN0 acceptance filter support register C0AFS ??16 ??16
~ ~
025A16 025B16 025C16 025D16 025E16 025F16
~ ~
Three-phase protect control register On-chip oscillator control register Pin assignment control register Peripheral clock select register CAN0 clock select register TPRC ROCR PACR PCLKR CCLKR 0016 000001012 0016 000000112 0016
~ ~
02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816
~ ~
I2C0 data-shift register I2C0 address register I2C0 control register 0 I2C0 clock control register I2C0 start/stop condition control register I2C0 control register 1 I2C0 control register 2 I2C0 status register S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 ??16 0016 0016 0016 000110102 001100002 0016 0001000X2
~
02FD16 02FE16 02FF16
~
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.7. SFR Map (7 of 11)
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Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16
Register Time measurement, Pulse generation register 0 Time measurement, Pulse generation register 1 Time measurement, Pulse generation register 2 Time measurement, Pulse generation register 3 Time measurement, Pulse generation register 4 Time measurement, Pulse generation register 5 Time measurement, Pulse generation register 6 Time measurement, Pulse generation register 7 Pulse generation control register 0 Pulse generation control register 1 Pulse generation control register 2 Pulse generation control register 3 Pulse generation control register 4 Pulse generation control register 5 Pulse generation control register 6 Pulse generation control register 7 Time measurement control register 0 Time measurement control register 1 Time measurement control register 2 Time measurement control register 3 Time measurement control register 4 Time measurement control register 5 Time measurement control register 6 Time measurement control register 7 Base timer register Base timer control register 0 Base timer control register 1 Time measurement prescale register 6 Time measurement prescale register 7 Function enable register Function select register Base timer reset register Count source division register
Symbol G1TM0,G1PO0 G1TM1,G1PO1 G1TM2,G1PO2 G1TM3,G1PO3 G1TM4,G1PO4 G1TM5,G1PO5 G1TM6,G1PO6 G1TM7,G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV
After reset ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0016 0016 0016 0016 0016 0016 0016 0016 ??16 ??16 0016 0016 0016 0016 0016 0016 ??16 ??16 0016
Interrupt request register Interrupt enable register 0 Interrupt enable register 1
G1IR G1IE0 G1IE1
??16 0016 0016
NMI digital debounce register Port P17 digital debounce register
NDDR P17DDR
FF16 FF16
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.8. SFR Map (8 of 11)
Rev.0.30 2004.06.15 REJ03B0072-0030Z page 23 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Register
Symbol
After reset
Timer A1-1 register Timer A2-1 register Timer A4-1 register Three phase PWM control register 0 Three phase PWM control register 1 Three phase output buffer register 0 Three phase output buffer register 1 Dead time timer Timer B2 Interrupt occurrence frequency set counter Position - data - retain function control register
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF
??16 ??16 ??16 ??16 ??16 ??16 0016 0016 0016 0016 ??16 ??16 XXXX00002
Port function control register
PFCR
001111112
Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate register SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate register
IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG
00XXX0002 0016 ??16 010000002 ??16 ??16 010000002 ??16
UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate register UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
0016 000X0X0X2 X00000002 X00000002 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2
Note 1 :The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.9. SFR Map (9 of 11)
Rev.0.30 2004.06.15 REJ03B0072-0030Z page 24 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-dowm flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 transmit/receive mode register UART0 bit rate register UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2
Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
After reset 0016 0XXXXXXX2 0016 0016 0016 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 0016 0016 0016 0016 0016 00??00002 00?X00002 00?X00002 X00000002 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 X00000002
CRC snoop address register CRC mode register DMA0 request cause select register DMA1 request cause select register CRC data register CRC input register
CRCSAR CRCMR DM0SL DM1SL CRCD CRCIN
??16 00XXXX??2 0XXXXXX02 0016 0016 ??16 ??16 ??16
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.10. SFR Map (10 of 11)
Rev.0.30 2004.06.15 REJ03B0072-0030Z page 25 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
4. Special Function Register (SFR) MAP
Address
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Register A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 A/D register 7
Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
After reset ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2
A/D trigger control register A/D status register 0 A/D control register 2 A/D control register 0 A/D control register 1
ADTRGCON ADSTAT0 ADCON2 ADCON0 ADCON1
XXXX00002 00000X002 0016 00000???2 0016
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register
P0 P1 PD0 PD1 P2 P3 PD2 PD3
??16 ??16 0016 0016 ??16 ??16 0016 0016
Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
??16 ??16 0016 0016 ??16 ???X????2 0016 000X00002 ??16 0016
Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register
PUR0 PUR1 PUR2 PCR
0016 0016 0016 0016
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
Figure 4.11. SFR Map (11 of 11)
Rev.0.30 2004.06.15 REJ03B0072-0030Z page 26 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
5. Package
5. Package
64P6Q-A
EIAJ Package Code LQFP64-P-1010-0.5
Recommended
JEDEC Code - Weight(g) Lead Material Cu Alloy
Plastic 64pin 1010mm body LQFP
MD
e
HD D
48 33
49
32
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
64
17
1
16
A e F L1
A2
A3
A1
y
b
x y b2 I2 MD ME
x
M
L Detail F
Lp
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 0.5 - - 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 - - 0.6 0.75 0.45 0.25 - - - - 0.08 - - 0.1 - 0 10 - - 0.225 1.0 - - - - 10.4 - - 10.4
HE
E
80P6Q-A
EIAJ Package Code LQFP80-P-1212-0.5 HD
Recommended
JEDEC Code - Weight(g) 0.47 Lead Material Cu Alloy
c
Plastic 80pin 1212mm body LQFP
MD
e
80
61
1
60
b2
D
l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
20
41
21
40
A F e
A2
L1
A3
x y b2 I2 MD ME
x
M
y
A1
Detail F
Lp
Rev.0.30 2004.06.15 REJ03B0072-0030Z
page 27 of 30
c
b
L
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 11.9 12.0 12.1 11.9 12.0 12.1 0.5 - - 13.8 14.0 14.2 13.8 14.0 14.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 10 - 0.225 - - - - 0.9 12.4 - - - - 12.4
HE
E
ME
ME
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
6. Functional differences
6. Functional differences
6.1 Functional differences between Normal-ver. and T-ver./V-ver. of M16C/29 group
Item Reset
Detailed Item M16C/29(Normal-ver.) M16C/29(T-ver./V-ver.) Voltage Detection Circuit Available Not available (Function of 001916, 001A16, (Power supply detection register 1, (Reserved register) 001F16) Power supply detection register 2, Power supply down detection interrupt register)
Note. Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.30 2004.06.15 REJ03B0072-0030Z
page 28 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
6. Functional differences
6.2 Functional differences between M16C/28 group and M16C/29 group (Normal-ver.)
Item Clock Protect
Detailed Item Clock Output Function PRC0 bit function
Interrupt
IFSR20 bit of IFSR2A register b1 bit of IFSR2A register Nothing is assigned (When write, set to "0") b2 bit of IFSR2A register Nothing is assigned (When write, set to "0") Key input interrupt
M16C/28(Normal-ver.) Not available (reserved bit) Enable wrtite to CM0, CM1, CM2, POCR, PLC0, PCLKR registers Must be set to "1"
M16C/29(Normal-ver.) Available (Clock output function select bit) Enable write to CM0, CM1, CM2, POCR, PLC0, PCLKR, CCLKR registers Must be set to "0" Interrupt request cause select bit (0:A/D conversion 1:Key input) Interrupt request cause select bit (0:CAN0 wakeup/error) CAN0 error A/D conversion/Key input interrupt Available (Port function control register) 27 channels (AN30 to AN32 available) Available Available Available (1channel) Available (1 curcuit) P93/AN24/CTX P92/AN32/TB2IN/CRX P91/AN31/TB1IN P90/AN30/TB0IN/CLKOUT
Interrupr source of software interrupt number 13 Interrupr source of software interrupt number 14 Three-Phase Motor Three-phase/Port Output Control Timer Switch Function (035816) A/D Conversion Analog Input pins Delayed trigger mode 0 Delayed trigger mode 1 CAN Module 2.0B BOSCH compliant
A/D conversion interrupt Not available (Nothing is assigned) 24 channels (AN30 to AN32 not available) The product of the first edition and version A do not available The product of the first edition and version A do not available Not available (Related registers are not assigned) Not available (Related registers are not assigned) P93/AN24 P92/TB2IN P91/TB1IN P90/TB0IN
CRC Calculation CRC-CCITT and CRC-16 Pin Function 2 pin (80 pin version) 62 pin (64 pin version) 3 pin (80 pin version) 64 pin (64 pin version) 4 pin (80 pin version) 1 pin (64 pin version) 5 pin (80 pin version) 2 pin (64 pin version)
Note. Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.30 2004.06.15 REJ03B0072-0030Z
page 29 of 30
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/29 Group
6. Functional differences
6.3 Functional differences between M16C/28 group and M16C/29 group (T-ver./V-ver.)
Item Protect
Detailed Item PRC0 bit function
Interrupt
CAN Module Pin Function
IFSR20 bit of IFSR2A register b1 bit of IFSR2A register Nothing is assigned (When write, set to "0") b2 bit of IFSR2A register Nothing is assigned (When write, set to "0") Interrupr source of software Key input interrupt interrupt number 13 Interrupr source of software A/D conversion interrupt interrupt number 14 2.0B BOSCH compliant Not available (Related registers are not assigned) 2 pin (80 pin version) P93/AN24 62 pin (64 pin version) 3 pin (80 pin version) P92/TB2IN 64 pin (64 pin version)
M16C/28(T-ver./V-ver.) Enable wrtite to CM0, CM1, CM2, POCR, PLC0, PCLKR registers Must be set to "1"
M16C/29(T-ver./V-ver.) Enable write to CM0, CM1, CM2, POCR, PLC0, PCLKR, CCLKR registers Must be set to "0" Interrupt request cause select bit (0:A/D conversion 1:Key input) Interrupt request cause select bit (0:CAN0 wakeup/error) CAN0 error A/D conversion/Key input interrupt Available (1channel) P93/AN24/CTX P92/AN32/TB2IN/CRX
Note. Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.30 2004.06.15 REJ03B0072-0030Z
page 30 of 30
REVISION HISTORY
Rev. Date Page 0.20 Apri/ 10/ 04 0.30 Jun/15/04 2,3 4,5 7 8 11,12 14 15 16 17,18 22 23 26 27 28 to 30
M16C/29 Short Sheet
Description Summary
First edition Table 1.2.1 and 1.2.2 are partly revised. Figure 1.3.1 and 1.3.2 are integrated descriptions. Table 1.4.4 is added. Figure 1.4.2 is added. Table 1.6.1 and 1.6.2 are integrated descriptions. Note 2 in Figure 3.1 is added. The Chapter "3. Memory" and Figure 3.1 are integrated descriptions. Figure 4.1 is partly revised. Figure 4.2 and 4.3 are integrated descriptions. Figure 4.7 is integrated descriptions. Figure 4.8 is partly revised. Figure 4.11 is integrated descriptions. 64P6Q-A package is revised. The Chapter "6. Functional differences" is added.
A-1
M16C/26A Group
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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